Wireless sensor networks have the potential to impact society through applications from environmental and health monitoring, to military surveillance. Network nodes are designed for extremely long lifetimes, and often rely on energy harvesting or scavenging devices for power, as well as a battery backup, limiting the available average power to that of a few μW to mW at the most. Silicon nanowires may be integrated with existing semiconductor processes for the eventual replacement of the planar CMOS transistor, and could be useful in a system-on-chip (SOC) sensor node architecture due to their proven usefulness in sensing, solar cell, and solid-state laser applications. We explore the circuit design aspects of a proposed near-term hybrid nanowire-CMOS process targeted for a sensor network node's digital signal processing (DSP) array. A reconfigurable interconnect for the DSP was designed, and accurate wiring capacitance models were developed to optimize the bus width and routing channel over multiple technologies. The design was then fabricated and tested in 0.25μm technology. A Reconfigurable Interconnect Tiled Array Simulator (RITAS) was developed to model the fabricated array. Results indicate that leakage becomes the largest power consumer when ported to a 22nm process. Nanowire transistors embedded within the metal interconnect are suggested to combat the growing leakage and short channel effects associated with end-of-roadmap CMOS technology. Three nanowire transistor structures are described and simulated to produce SPICE model cards in 90nm and 22nm nodes for use in a circuit simulator. Utilizing the suggested integrated nanowire transistor models within RITAS determines that power may be reduced by up to 44% in the active mode and 79% during sleep mode for the DSP architecture. Circuit design opportunities for the nanowire transistors are identified within power gating circuitry. A quantitative study showcases the benefits of nanowire transistors over multiple topologies, process nodes, voltages, and sizings, over several metrics. Results show leakage reductions up to two orders of magnitude in some topologies over similar planar-based designs. These benefits are shown to come with comparable delay penalties, and fast wakeup times.