With demanding requirements of ever-increasing data storage and multi-media intensive content, the next-generation wireless communication system has to accommodate multi-gigabit applications such as data transfer and HD video streaming. However, the traditional transceiver architecture with power-hungry data–converters and DSP modems limits the portability of the device operating at such high-speed. In order to incorporate this functionality in a more versatile, reliable and affordable way, alternative system architectures are investigated to achiever low-power multi-gigabit demodulation in CMOS technologies. With the availability of wideband spectra, both UWB and millimeter-wave frequency bands (60 GHz, 70 GHz, 80 GHz and 90 GHz) provide the perfect vehicles to bring the ultra-portable multi-gigabit WPAN and WLAN applications into reality.

This dissertation presents system and circuit development of the low-power multigigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of −38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.