The continuous and aggressive scaling of CMOS devices to satisfy performance demands has brought with it the challenge of increased power dissipation and aggravated thermal issues. The average junction temperature will continue to rise due to increase in device-density and clock-frequency of current-generation processors. Further progress in the IC design industry will be severely constrained by the availability of cost-effective cooling solutions and the ability to account for heat as a source of performance variability in on-chip microelectronic elements. High-resolution, low-power and process-tolerant thermal monitoring circuits will be required to capture the extreme thermal gradients observed across the die and provide the necessary feedback to Dynamic Thermal Management (DTM) schemes.

Broadly, this dissertation presents two bodies of work: (1) Temperature effects on super-threshold logic and sub-threshold circuit design metrics and (2) Design of low-power, high-sensitivity thermal and process sensing systems and their test-chip implementation in 45nm CMOS-SOI technology using an IBM design-kit procured from MOSIS.