Indium phosphide heterojunction bipolar transistors are able to achieve higher bandwidths at a given feature size than transistors in the Silicon material system for a given feature size. Indium phosphide bipolar transistors demonstrate higher breakdown voltages at a given bandwidth than both Si bipolars and field effect transistors in the InP material system. The high bandwidth of InP HBTs results from both intrinsic material parameters and bandgap engineering through epitaxial growth. The electron mobility in the InGaAs base and saturation velocity in the InP collector are both approximately three times higher than their counterparts in the SiGe material system. Resistance of the base can be made very low due to the large offset in the valence band between the InP emitter and the InGaAs base, which allows the base to be doped on the order of 1020 cm-3 with negligible reduction in emitter injection efficiency.
This thesis deals with type-I, NPN dual-heterojunction bipolar transistors. The emitters are InP, and the base is InGaAs. There is a thin (∼ 10 nm) n-type InGaAs “setback” region, followed by a chirped superlattice InGaAs/InAlAs grade to the InP collector. The setback, grade, and collector are all lightly doped n-type. The emitter and collector are contacted through thin (∼ 5 nm) heavily doped n-type InGaAs layers to reduce contact resistivity.
The primary focus of this work is increasing the bandwidth of InP HBTs through the proportional scaling of the device dimensions, both layer thicknesses and junction areas, as well as the reduction of the contact resistivities associated with the transistor. Essentially, all RC time constants and transit times must be reduced by a factor of two to double a transistor's bandwidth. Chapter 2 describes in detail the scaling laws and design principles for high frequency bipolar transistor design. A low-stress, blanket sputter deposited composite emitter metal process was developed. Refractory metal base contacts were investigated with UCSB grown epitaxial material and the fabrication of transmission line model structures. Electron beam lithography processes were developed and employed for both emitter and base layers. Epitaxial designs were scaled and revised, and grown by a commercial vendor. These process developments are detailed in Chapter 3.
Transistor electrical characteristics were measured using a semiconductor parameter analyzer at DC and network analyzers for RF measurements at frequencies up to 220 GHz. Both on- and off-wafer network analyzer calibration structures were designed and fabricated, and the calibration techniques were compared. New structures for transmission line model measurements of contact resistivity have been designed and used in the measurement of new ohmic contact processes. Measurement techniques are detailed in Chapter 4.
Two transistor results are presented in Chapter 5. For each device, epitaxial designs are presented, and band diagrams, both without current flow and under peak bias conditions are shown. The processes used to fabricate each transistor are detailed. For the first result, referred to as DHBT 43, fτ = 360 GHz and fmax > 800 GHz was obtained with 200 nm wide emitter-base junctions and 150 nm thick collectors. For the second result, referred to as DHBT 60, fτ = 530 GHz and fmax = 750 GHz was obtained with 150 nm wide emitter-base junctions and 70 nm thick collectors. Both transistors feature a refractory emitter contact, and the second result uses electron-beam lithography to narrow the emitter-base and base-collector junction widths. DC measurements of common-emitter I-V curves and Gummel plots are used to extract device parameters like breakdown voltage, current gain, and base and collector ideality constants. On-wafer TLM structures are used to extract device base and collector resistance. S-parameter measurements at RF frequencies are used to extract cutoff frequencies fτ and fmax, as well as device parameters necessary to generate hybrid-& equivalent circuit models of the devices. These measurements and device results are detailed in Chapter 5.
Chapter 6 summarizes the progress and results of this work, and identifies the critical challenges and limits to further device scaling. Fabrication processes are proposed for the next generation of InP bipolar transistors.