In the past decade, chip manufacturers have begun producing chips with more and more cores, rather than increasing clock frequency as a means to increase chip performance. However, the performance of applications is often not improved by the addition of multiple cores, especially when the applications require frequent communication. This occurs when the overhead generated by communication and contention for resources outweighs the benefit of dividing the computation between the cores. One common class of applications that has large communication overhead is parallel discrete event simulation.

Discrete event simulation is a technique commonly used to model physical systems as a series of events which occur at discrete points in time. These simulations are commonly parallelized when either the state of the model is too large to fit into the memory of a single processor, or the runtime of the simulation is too long. Parallel discrete event simulation has two main sources of overhead, time synchronization and message passing.

The goal of this thesis is to decrease these sources of overhead for parallel discrete event simulators on multi-core systems through the use of specialized hardware. By using the proposed specialized hardware units for both time synchronization and message passing, the communication required by the simulation will be greatly reduced, decreasing the runtime of the simulation.

The contributions of this work are as follows: (1) We present the design for a Global Synchronization Unit, which performs the time synchronization for parallel discrete event simulators on multi-core systems. We have demonstrated a 40% reduction in runtimes for a parallel network simulation using this specialized hardware on up to 32 cores. (2) We have also introduced a software implementation of the Global Synchronization Unit, which runs as a separate thread or process. This software implementation can be used when the cost of specialized hardware is prohibitive or on existing multi-core systems. (3) We present the design for two hardware units, the Atomic Shared Heap and Atomic Message Passing, which are used together to perform zero-copy message passing on multi-core systems. We have demonstrated a 16% decrease in runtime using these devices in a parallel simulation on up to 32 cores. (4) Finally, we introduce software implementations of the Atomic Shared Heap and Atomic Message Passing, with each implemented as a separate thread or process. These software implementations can be used together to perform zero-copy message passing on existing multi-core systems or when the cost of specialized hardware is too great.