With the revolution of the digital CMOS design, the CMOS technology has become the dominant process technology in today's semiconductor industry. However, as the channel lengths of the MOS transistors reduce with the introduction of each CMOS process node, the intrinsic gain (gm × rds) of the MOS transistors decreases. As this trend continues, the high-gain amplifiers required for accurate residue amplification in pipelined ADCs will not have enough open-loop gain to provide sufficient accuracy. Therefore, achievable accuracy or speed must be lowered. On the other hand, new circuit architectures and clever use of the readily available powerful DSP capability can be exploited to decouple the gain, accuracy, and speed requirements.

The main objective of this research was to develop a background calibration technique that would enable the design of a 2-stage pipelined ADC with an open-loop residue amplifier. This technique and its variations can potentially eliminate the need for high-gain amplifiers in pipelined ADCs, which is especially vital for high-performance ADC design in modern fine-line CMOS technologies.

Moreover, a double-switching switched-buffer SHA architecture was proposed and demonstrated. The proposed double-switching architecture eliminates the hold-mode feed-through. Therefore, the SHA maintains its linearity with input frequencies as high as the Nyquist rate.