As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. If this uncertainty is not properly handled, it may become the bottleneck of CMOS technology improvement. This dissertation proposes novel techniques to model, analyze, and optimize power and performance of FPGAs and ASICs considering process variation. This dissertation focuses on two aspects: (1) Process and architecture concurrent optimization for FPGAs; (2) Statistical timing modeling and analysis.

To perform process and architecture concurrent optimization, an efficient and accurate FPGA power, delay, and variation evaluator, Ptrace, is proposed. With Ptrace, we present the first in-depth study on device and FPGA architecture co-optimization to minimize power, delay, area, and variation considering hundreds of device and architecture combinations. Furthermore, to enable early stage process and architecture co-optimization without stable device models, we develop transistor level and circuit level power, delay, and reliability models and incorporate them with Ptrace. With the extended Ptrace, we perform architecture and process parameters concurrent optimization for FPGA power, delay, variation, and reliability.

To perform statistical timing modeling and analysis, we first present an efficient and accurate statistical static timing analysis (SSTA) flow for non-linear cell delay model with non-Gaussian variation sources. All operations in this flow are performed by analytical equations without any time consuming numerical approach. Then, to further improve the efficiency and accuracy of statistical timing analysis, we develop a new die-level spatial variation model which accurately models the across-wafer variation. Besides modeling spatial variation, mean and variance uncertainty introduced by limited number of samples is another problem in SSTA. To solve this problem, we evaluate the confidence for statistical analysis and estimate the guardband value to ensure a target confidence.

To the best of our knowledge, this dissertation is the first novel study of device, process, and architecture concurrent co-optimization for FPGA power, delay, variation, and reliability; and is the first work to model across-wafer variation at die-level and to consider confidence guardband in statistical analysis.