This dissertation presents design and implementation of the high speed direct digital frequency synthesizer (DDS) and variable-frequency oscillator (VFO). DDS is a digital technique for frequency synthesis, waveform generation, sensor excitation, and digital modulation/demodulation in modern communication systems. The VFO can be used as the reference clock of the DDS system, either standalone or combined with other phase-locked-loop (PLL) components.

DDS provides many advantages including fine frequency-tuning resolution, continuous-phase switching and accurate matched quadrature signals. DDS can directly generate and modulate signal at microwave frequencies. A high-speed DDS can be significantly simplified the transceiver architecture. Thus the cost of radio and radar systems can be reduced considerably.

Ultrahigh speed DDS over GHz is demanding for modern radar and communication systems. This research proposes work on designing ultrahigh speed DDS chips with sine-weighted digital-to-analog converter (DAC) in Silicon Germanium (SiGe) BiCMOS technology and using a VFO as the reference clock. Sine-weighted DAC is necessary for ultrahigh speed DDS design to overcome the speed limitation of the ROM lookup table (LUT) in conventional DDS designs. The sine-weighted DAC replaces ROM LUT and linear DAC to perform the phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. A segmented sine-weighted DAC is designed and implemented to achieve 10-bit amplitude resolution.

Due to the code dependent and frequency dependent non-ideal effects from the sine-weighted DAC, the unwanted harmonics and spurs of the DDS outputs have more significant impacts on the whole systems. In this dissertation, the spurs and harmonics from different sources such as truncation errors, limited DAC amplitude resolutions and non-ideal effects of DAC will be discussed.

Four fabricated silicons are implemented in SiGe BiCMOS technology and discussed in the dissertation, including three DDSs and one VFO. The first DDS is a 11-bit 8.6 GHz ROM-less DDS with 10-bit segmented sine-weighted DAC. The second one is a 9-bit 2.9 GHz ROM-less DDS with direct digital modulation capabilities. The last DDS is a 24-bit 5.0 GHz ROM-less DDS with direct digital modulation capabilities. Besides the DDS designs, an 8.7–13.8 GHz VFO, implemented by a transformer coupled current-controlled varactor-less oscillator with quadrature outputs, will be presented in this dissertation, too. Circuit and layout designs of DDS building blocks such as current mode logic (CML), pipeline accumulator, carry look-ahead adder/accumulator, ripple-carry adder/accumulator and segmented and non-segmented sine-weighted DAC are presented. The quadrature current-controlled oscillator (QCCO) is discussed as well as the design and implementation of the on-chip transformer.