This thesis presents a VLSI design methodology utilizing a buffer-based data flow to reduce interconnect resources and to synchronize the data transfer between different processing elements (i.e. between processors/between a processor and a hardware logic). The buffer-based dataflow is a novel design representation suitable for implementing data-centric applications. Since the buffer-based dataflow isolates the functional execution and data transfer of each node by using parameterized buffer controllers, it is helpful for reducing overall design time and for increasing reconfigurability.

We first propose a sharing methodology which reduces the buffer memory and the number of buses used in the realization of a buffer-based dataflow. Buffer controllers in a buffer-based dataflow represent the interconnects for data transfers between nodes. In order to achieve interconnect resource reduction, we control data transfers by using buffer lifetimes and activity times parameterized in a buffer-based dataflow. In addition, the proposed methodology finds the sharing case that consumes the minimum energy within the search range determined by the costs of buffers and buses.

We also propose a mapping methodology for the case where nodes of a buffer-based dataflow are realized as programs running on processors. From the buffer-based dataflow and estimated execution times of functional blocks and data transfers, the proposed methodology creates a mapped partition and generates the template code which runs on the processors of a target platform. We also use a processor initiation scheme to prevent wrong operations from happening when actual execution takes longer than estimated.

Finally, we evaluate the proposed sharing methodology with dataflow graphs representing data-centric applications. Also, our proposed mapping methodology and the generated template code are evaluated with the SystemC model and Xilinx ISE. The proposed methodologies are applicable to the high-throughput implementation of VLSI systems, for which the simplification of control structure is critical, and to the design of reconfigurable system-on-chip (SoC).