This dissertation seeks to understand the unique physics of, to explore non-conventional ways of designing, and to gain insights on the performance of nanoscale double-gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes modeling of drain-induced charge enhancement, suggesting a novel way of adjusting the threshold voltage of nanoscale DG MOSFETs via limited source/drain dopants in the channel, comparing the analog/RF performance of DG FinFETs and bulk-silicon MOSFETs, and studying and designing ultrathin-BOX FD/SOI MOSFETs with comparisons to DG FinFETs.

Drain-induced charge enhancement (DICE) is a short-channel effect which is unique to nanoscale DG MOSFETs with undoped bodies because of their significantly high carrier mobility. We model this effect, and study its effect on the current, charge, capacitance, and transcapacitance of DG MOSFETs. We find that DICE is a beneficial effect because it increases current without significantly affecting gate capacitance.

Adjusting the threshold voltage of DG MOSFETs with undoped bodies for low-power and high-performance applications is a challenging task. We propose a design approach in which limited densities of source/drain dopants in the channel can be used to effect an adjustment of threshold voltage in DG MOSFETs, while maintaining low sensitivities to random-doping fluctuations.

Most of the current literature on the analog/RF performance of DG MOSFETs is based on experimental results, with little physics-based explanation of the results. We give physical insights on the design and performance of DG MOSFETs for analog/RF applications, and compare them with bulk-silicon MOSFETs. We find that like for digital applications, DG MOSFETs have superior analog performance than that of conventional planar bulk-silicon MOSFETs.

Recently, there has emerged a considerable interest in planar FD/SOI MOSFETs with ultra-thin BOX. We give our physical insights, based on device simulations, on the design and performance of ultra-thin-BOX FD/SOI MOSFETs, and check their scalability toward the end of the CMOS roadmap compared with DG FinFETs.