As CMOS technology continues to advance to smaller feature sizes, digital-logic circuits use less power while becoming faster and smaller. On the other hand, wireless analog circuits often benefit from the higher speed, but suffer various ill effects such as low voltage headroom making conventional analog circuits difficult to design. Integrating wireless analog functionality onto high-volume CMOS greatly reduces the size and cost of wireless devices, which is motivating a tsunami of engineering innovation. Many innovations exploit the high-performance, high-density digital circuits available in CMOS. Analog circuits with only modest native performance can be made to deliver high performance by using digital calibration and correction. In this work we present three wireless analog functions in CMOS: a linearized varactor, phase-locked loop (PLL), and power amplifier (PA).

Many radio frequency (RF) circuits use varactors that have nonlinear capacitance-tuning characteristics. To improve the tuning linearity at the cost of a lower capacitance tuning ratio, many circuits tune a large varactor over a small portion of its tuning range. We demonstrate here that a conventional varactor’s performance can be improved by breaking it into smaller, independently tuned, parallel segments. This increased tuning dimensionality can enable a varactor to be realized with a high tuning linearity over most of its tuning range while reducing the capacitance’s dependence on the instantaneous RF-input signal.

In many applications, PLLs need to have a large fine-tuning frequency range to accommodate changes in environmental conditions such as temperature and supply. Typically, the fine-tuning sensitivity of the varactor in a PLL’s voltage-controlled oscillator is proportional to its fine-tuning range, which makes the PLL more susceptible to picking up noise and spurs. A new dual-path PLL architecture is introduced that uses a softly switched varactor array in a digitally controlled integral path. This architecture decouples the PLL’s tuning sensitivity from its tuning range, thus achieving a very low fine-tuning sensitivity.

To realize high spectral efficiency, many wireless schemes modulate both the RF carrier’s phase and envelope, necessitating the use of a linear PA. Hence battery powered wireless transceivers require a PA that is both linear and power efficient, which, over even a modest dynamic range, would be difficult to implement in CMOS. Various PA linearization methods are discussed leading to the chosen polar-feedback method. The designs, implementations and measurements for some key blocks required for a PA with polar feedback are presented and the challenges remaining to implement a working system are discussed.