During the last decade there has been unprecedented growth in the use of portable wireless communications devices for applications as diverse as medical implants, industrial inventory control, and consumer electronics. If these communication devices are to be low power, flexible, and reconfigurable, new radio architectures are needed which take advantage of the major strength of state-of-the-art digital manufacturing processes; that is the ability to build large, complex low power signal processing circuits, with extremely fast clocking speeds. However, traditional radio architectures rely on analog techniques which are ill suited for the use in modern highly integrated digital systems.

A critical component of a radio system is the frequency synthesizer, a circuit which can accurately synthesize and modulate high frequency signals. Traditional synthesizers still utilize a significant amount of analog circuitry. In this work, techniques are developed to replace this analog circuitry with digital equivalents. To do this, a digital phase detection scheme for a Fractional-N Phase Lock Loop (FPLL) is presented. The all-digital phase detector can be used as an alternative to a conventional analog-intensive phase detector, charge pump and loop filter blocks.

Another limitation of traditional synthesizers is the difficulty in modulating the frequency of the output signal at speeds larger the FPLL's bandwidth. A new technique is developed for modulating the output frequency of the FPLL at rates significantly faster than the loop bandwidth would typically allow. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated. The new scheme does not compromise on the frequency accuracy of the output signal. The key ideas presented have been proven in a proof of concept design. A prototype 2.2GHz fractional-N synthesizer, incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142kHz, an FSK modulation rate of 927.5kbs is achieved. The prototype is implemented in 0.13μm CMOS and consumes 14mW from a 1.4V supply.