Many communication, sensor and consumer electronics applications require high-accuracy, low-power ADCs to interface with digital signal processing cores. The continuing demand to minimize power dissipation, while at the same time increasing converter speed and accuracy, poses difficult challenges in modern ADC design. Digital calibration techniques have been shown to relax the requirements in the analog components of ADCs at the expense of increased digital complexity. Recent work has shown significant power savings can be achieved using these techniques. As process technologies continue to scale, digital calibration will become an even more attractive tool in the design of high performance ADCs. A digital calibration scheme that allows a switched-capacitor Delta-Sigma ADC to operate with significantly reduced power consumption is proposed. As power dissipation is reduced in the integrators, nonlinear settling errors cause increasing harmonic distortion. The calibration technique uses a polynomial approximation to correct the nonlinearity and reduce distortion in the post-filtered digital output. With calibration, experimental results over a signal bandwidth of 1 MHz yield a peak SNDR of 75 dB, a THD of −90 dB and a SFDR of 94 dB. The power dissipation of the calibrated modulator is 5 mW at 2.4 V, saving 38% over a similarly performing uncalibrated output. The active area is 0.39 mm² in 0.25µm CMOS.