Transistor scaling has driven the development of semiconductor industry over the last few decades. However, scaling has also generated numerous challenging problems over technology nodes such as power consumption and circuit variability. Power and circuit variability has continuously increased over technology generations, becoming significant concerns for circuit designers. Various circuit techniques have been developed to address these issues.

Recently, ultra-low power or energy systems are becoming more and more popular. These systems include implantable biomedical electronics, wireless sensor nodes, RFID tag, and many portable electronics. For these applications where minimal energy consumption is the primary design constraint, sub-threshold logic circuits are becoming increasingly accepted since they consume roughly an order of magnitude less power, compared with normal strong-inversion operation.

The first half of this thesis makes several contributions that facilitate reliable sub-threshold circuit design. First, we present a device-size optimization method for sub-threshold circuits utilizing reverse short-channel effect (RSCE) to achieve high drive current, low device capacitance, less sensitivity to random dopant fluctuations, better sub-threshold swing, and improved energy dissipation. Second, we apply the proposed sizing method to SRAMs and propose several circuit techniques for subthreshold SRAMs that improve SRAM cell stability, writability, bitline sensing margin, and power reduction. By combining these proposed circuit techniques, we demonstrate two fully functional sub-threshold SRAMs in 130nm process technology.