As mainstream manufacturing process migrates to 40nm and beyond, designs are becoming more sensitive to the various variation sources. Due to the drive of low power application, supply voltage has been scaled aggressively. It does not only make the design more sensitive to change of voltage, but also makes traditionally secondary factors, such as temperature, impact the design performance more severely. As devices are placed more densely on the die, the design uncertainty is increasing due to various effects, such process variation, cross-talk, etc. The presence of design uncertainty makes the performance on silicon to be more statistically distributed. Thus, the test uncertainty increases, and maintaining the test quality is more difficult than ever. A more advanced test methodology is required to address the test uncertainty. This dissertation first discusses the design challenges that ASIC is facing, and then presents a study in silicon speed binning, which ASIC is adapting. Next we propose a framework to screening out defective samples and quantify amount of failure risk in passing samples with and without known good and bad samples. The framework can also guide test optimization based on statistical characteristic observed in test data.