Abstract:

The phenomenal growth of the semiconductor industry has made the design of integrated circuits a daunting task. Due to the non-stop miniaturization of the design process, and the increase in the clock speed, the design of the clock network which is responsible of synchronizing the various design components has become very challenging. The ASIC design flow defers the design of the clock network until late in the design cycle when the cell placement is done and the locations of the registers are known. Up until that stage, all timing arid power decisions that rely on the clock network are handled with estimates and ad-hoc methods. Worst case estimates of the clock timing makes convergence on the timing of high-end designs very difficult. In addition, power has become one of the most critical design constraints. Knowing that the clock network consumes more than 40% of the power budget, deferring the design and implementation of the clock until late in the design flow causes numerous design iterations and negatively affects the convergence and performance of the design.

In this work, we examine the design factors that affect the design, implementation, and optimization of ASIC designs. We focus on the design and implementation of the power and clock networks as the two most important signals in the design, arid study the various electrical and physical factors that affect their performance and reliability. We propose a new clock-driven design methodology that tackles the design of the clock network early in the design cycle before the implementation of the logic. The proposed methodology relies on designing a hybrid clock network that provides predictability and robustness to the design flow.

To break the reliance of the clock design on cell placement, we propose new algorithms that place the clock sinks (registers/latches) before the placement of the rest of the logic. Once the clock network is designed, laid out, and optimized, it drives the implementation of the entire design.

Nanometer designs operate under very tight design margins and constraints. Worst case decisions should be avoided whenever possible to successfully implement, the design and meet its design targets. By tackling the clock network design early in the design cycle, detailed information about the timing characteristics and power consumption of the clock winch is the biggest consumer of power in the design is known. This design approach facilitates relaxing the tight design budgets that are based on worst case decisions and enable a more successful physical synthesis of the design.