Adaptive energy and performance adjustment, like dynamic voltage scaling and adaptive transistor body bias, is an attractive method to improve the effective power efficiency of a circuit. Unfortunately in modern technologies body bias is not very effective in controlling leakage current. In this thesis, we propose an alternative approach to the in situ adjustment of the energy-performance point of the design. We first show how the effective threshold of transistors can be adjusted over a wide range using skewed supplies. Leveraging this method for pure static logic is difficult, so we create a new circuit architecture that is intrinsically faster than static circuits, and more importantly, can use skewed supplies to tune both dynamic and leakage power of the system over a wide range. As an example, we describe how the proposed architecture can be used to implement FPGA chips that can be programmed in the field to be low power or high performance depending on the application. Measured results from a 90-nm CMOS test-chip indicate that much wider tuning range is possible using the new programmable interconnects compared to static interconnects. The key to this new logic family is the use of static external signaling, but internal pulse logic. Using pulses, even if they are internal to the gates, does complicate system performance analysis. We also include a discussion of the issues involved with the use of the proposed logic for general circuits and how to analyze the resulting system.