Numerous functional IP cores (processors, DSPs, memories, and peripherals) are integrated into modern System-on-chip (SOC) single chip designs. Based on the expectations of ITRS and many SOC experts, the billion-transistor and 10 Ghz era will arrive around 2012 with a feature size of about 50nm. On-chip communication requirements are accordingly being raised with the development of modern technology. The design of on-chip communication architectures is playing a more and more important role for these SOC designs. Efficient communication architectures are therefore needed for solving the communication contentions between the IP cores to avoid any degradation of system performance.

The research in this dissertation focuses on the new SOC on-chip communication architecture designs, including Static and Dynamic Fraction Control Buses for shared-bus communication architecture and Single- and Multi-level Central Caching communication architectures for Network-on-chip (NOC) architecture, which offer attractive solutions for the current communication problems and address shortcomings of existing communication architectures.

To demonstrate the benefits of the proposed architectures, several existing communication architectures were compared to the proposed architectures based on different application prototypes. Through experimentation it has been shown that the proposed architectures not only exhibit both hardware simplicity and system performance improvements, but also produce better performance in terms of bandwidth control and scalability properties for shared-bus architecture and communication throughput and latency for NOC architecture compared to the existing communication architectures.