The ever growing portable semiconductor market demands high performance analog-to-digital converters (ADCs) in terms of resolution and signal bandwidth with stringent requirements on the power consumption, in order to maintain a longer battery life. The analog circuitries are required to be integrated with the digital circuitries to provide system-on-chip solutions (SOCs). This leads to a need for analog circuitries to be implemented in digital technologies where high performance and precision devices do not exist. For the portable applications sigma-delta ADCs are preferred due to their high performance in the absence of precision components and low power consumption. The resolution of a sigma-delta ADC can be increased by increasing one or more of the three parameters; number of bits used for the flash, over-sampling ratio (OSR), and the order of the modulator. The increase in the number of bits is limited due to the exponential increase in the area consumption as well as the complexity of the implementation of the digital-to-analog converter (DAC) in the feedback loop. OSR can be increased by increasing the sampling frequency; however, this increases the power consumption of the analog circuits. Higher order of modulators can be achieved by either cascading low order modulators or increasing the number of integration loops in single loop architectures. Beyond 2^nd order, the single loop modulators exhibit stability problems. Due to this apparent trade-off, the system architecture and parameters have to be optimized to meet the desired system specifications. This research presents a new sigma-delta modulator architecture that utilizes 1^st order, two-path, time-interleaved modulator to obtain a 2^nd order noise shaping. The increase in the order of the modulator is achieved by cross-coupling of the quantization noise between two paths. The modulator architecture has the advantage of reducing the speed of the conversion by half, compared to traditional 2^nd order modulators. Therefore, it enables low power implementations for low OSR, wide bandwidth applications. Furthermore, the proposed 2^nd order modulator can be implemented with just one opamp. The reduction in active components enables further power savings. The sigma delta ADC is implemented and simulated using a 90nm CMOS technology.