In this thesis we study some optimization problems in device and circuit design, and efficient methods to solve them.

We consider the device design problem of determining the doping profile that minimizes base transit time in a bipolar junction transistor. We show that the problem can be formulated as a geometric program (GP), which can be solved (globally optimally) very efficiently using standard methods. The geometric programming approach extends to several cases, including the case of heterojunction bipolar junction transistors, in which the doping profile, as well as the profile of the secondary semiconductor, are to be jointly optimized.

We consider the circuit design problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimum allowed gate size. This problem is well known to be a GP, and can be solved using standard methods for small and medium size problems with up to several thousand gates. We describe a new custom method for solving this problem that handles far larger circuits, a million gates or more, and is far faster.

We consider the problem of choosing the arrival times at the nodes of a timing graph in order to maximize a concave utility function of the resulting slacks, given the delays on the edges and the arrival times at the source and sink nodes. This slack allocation problem is a convex optimization problem, and can be reliably (globally optimally) solved by Newton's method; but Newton's method does not scale beyond problems with a few thousand nodes. We develop a custom method that efficiently computes an accurate solution, and scales to problems with a million or more nodes.