Harvesting energy from environmental sources can extend the lifetime of wireless sensor network nodes beyond the limits of battery technology. However, the output power from an energy harvester is highly variable. This dissertation describes a domain-specific computational array which maximizes sensor availability by matching system power consumption to the obtainable scavenged energy through power scalable approximate signal processing. The array consists of distributed arithmetic (DA)-based functional units coupled with an island-style reconfigurable interconnection network. Each functional unit is capable of computing a set of linear and nonlinear core signal processing functions in an area efficient manner, which also minimizes leakage power. Sensor DSP applications, such as Finite-Impulse Response (FIR) filters, Fast Fourier Transform (FFT), rectangular-to-polar conversion, polar-to-rectangular conversion, and Taylor polynomial evaluation, are mapped onto the array through the reconfigurable interconnect structure. A low power sensor DSP chip of a 4x4 array has been designed and implemented to validate our architecture concepts and circuit techniques. The chip was fabricated in 0.25μm CMOS technology.