New requirements for on-board spacecraft processing systems demand solutions with high-end computation capabilities, reconfigurable logic for hardware acceleration and processing properties, as well as the ability to easily interface with different types of sensors and sub-systems. Additionally, it is desirable that the architecture of the systems be modular, easily deployable and versatile, while limited in weight and size.

This dissertation describes the AFRL-UNM High-End Reconfigurable Computer (HERC), a new multiprocessor architecture for use in high-performance on-board space applications. This architecture was developed to have modular and compact basic processing nodes, interconnected by high-speed communications links that aggressively embed most of their components in Field Programmable Gate Arrays (FPGA).

To investigate the properties of this architecture, a prototype was constructed and studied. Benchmarking applications were run on this prototype to characterize the performance of its embedded microprocessors, its memory system, its communications network, and the performance of the system in a multiprocessor context. This analysis is accompanied by comparisons to related architectures that identify the position the HERC occupies in an architectural space. Also, analyses of the power and resources utilized by this architecture were preformed. Using these analyses, the scalability of the HERC is predicted.