This research focuses on the design and analysis of on-chip phased-array receivers and transmitters in silicon technologies. Passive phase shifters have been widely used in conventional discrete implementations of phased-arrays which are based on transmit/receive modules in III-V technologies. However their large volume and high loss impose several challenging issues for on-chip integration. To leverage system optimizations of on-chip phased-arrays, active phase shifter architecture is primarily investigated in this dissertation. The active phase shifter utilizes a quadrature signal interpolation where the I/Q signals are added with appropriate amplitude and polarity to synthesize the required phase. The quadrature signal generator is a key element for accurate multi-bit phase states in the active phase shifter. To generate lossless wideband quadrature signals, a novel I/Q signal generator based on second-order L-C series resonance is developed. Active phase shifters with 4-bit and 5-bit control are then designed in 0.13-μm and 0.18-μm CMOS technologies and tested successfully for 6-26 GHz phased-arrays applications, featuring the smallest chip size ever reported at these frequencies with similar phase resolutions.

After successful demonstration of the active phase shifters, an eight-element phased-array receiver is developed in 0.18-μm SiGe BiCMOS technology for X- and Ku-band satellite communications. The phased-array receiver adopts corporate-feed architecture implemented with active signal combiners. The phased-array receiver is rigorously characterized including channel-to-channel mismatches and signal coupling errors from different channels. The on-chip phased-array designs are then extended to millimeter-wave frequencies. A four-element phased-array receiver and a sixteen-element phased-array transmitter are designed using the SiGe BiCMOS technology and tested successfully for Q-band applications. Wilkinson couplers are compactly integrated for linear coherent signal combining in the Q-band phased-array receiver. Also in the Q-band transmitter array, passive Tee-junction power dividers are integrated as a linear signal feed network. The power divider is based on a coaxial-type shielded transmission line utilizing three-dimensional metal stack, which leads to a compact corporate-feed network suitable for large on-chip arrays. The sixteen-element phased-array transmitter marks the highest integration of phased-array elements known to-date, proving a good scalability to a large array of the proposed phased-array architecture. Also, each phased-array design integrates all digital control units and presents the first demonstration of on-chip silicon phased-array at the corresponding design frequency, solving one of key barriers for low-cost and complex phased-arrays.