As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance and power consumption of processors by making the latency of circuits less predictable and thus requiring conservative design approaches and/or techniques to increase performance that often affect power consumption. In this dissertation, we introduce and study step-by-step a 16KB cache subsystem in 32-nm CMOS technology, at both circuit and architecture levels, aiming for a single-cycle process-variation resilient subsystem design in a 1GHz processor that is high performance and power efficient at the same time. We use expected-case simulations in addition to worst-case circuit analysis to establish the overall delay and power consumption due to process variations under both typical and worst-case conditions. The distribution of the cache critical-path delay and power consumption in the typical scenario was determined by performing Monte Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on the complete cache design. In addition to establishing the delay and power variations, we introduce an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design point, and allowing tradeoffs between power and performance to be controlled. We show that the proposed adaptive cache is transparent to other processor subsystems and has negligible power and area overhead compared to a conventional design. We also establish what the overall leakage power is due to process variations. The distribution of the cache leakage power was determined before and after incorporating state-of-the-art leakage optimizations. Simulation results show that our adaptive data cache is process-variation-resilient and can achieve on average 10% performance improvement on SPEC2000 applications in a superscalar processor, in conjunction with 6X reduction in the mean leakage power compared with a conservative design. Additional performance improvement potential exists in processors in which the data cache access is on the critical path, by allowing a more aggressive clock rate in the processor.