Superconductor electronics excel for high operation speed and low power consumption (several orders of magnitude lower than the equivalent semiconductor circuits). Rapid-Single-Flux-Quantum (RSFQ) circuits, in which information is stored in superconductor loops as tiny magnetic flux quanta and transferred as several picosecond-wide voltage pulses with quantized area ([special characters omitted]V(t)dt = [special characters omitted] = 2.07mV·ps), are demonstrated to work at a few tens of gigahertz with the current niobium process and has the potential to work up to a few hundred gigahertz with technology scaling. A large superconductor RSFQ system or a hybrid system combined with the low-power high-density cryogenic CMOS memory can be realized with a multi-chip module (MCM) packaging technique.
The goal of this thesis project is to design and to experimentally demonstrate 20–50 GHz operation of a 1:8 demultiplexer (DEMUX) and an 8:1 multiplexer (MUX). DEMUX and MUX are important interface circuits that are required to take advantage of the ultra-high speed of the RSFQ logic. They are required to interface the superconductor and the lower-speed semiconductor circuits in a hybrid system. In a superconducting MCM system, the DEMUX and MUX can be used to convert the data rate between chips.
The speed of RSFQ circuits scales with the process technology. An analysis is done to show that the maximum speed of RSFQ circuits is proportional to the shunted Josephson junction's critical current times its shunt resistance (IcR) value. Furthermore, IcR is proportional to the square root of the junction's critical current density (Jc 1/2) in the low-Tc niobium process. Superconductor integrated circuits using a 1 kA/cm2, 3.5 μm niobium fabrication technology can operate up to 30–40 GHz. Simulations reveal that simple RSFQ elements and gates based on a 6.5 kA/cm2 technology can operate up to 70–100 GHz. With typical circuit parameters, the minimum features are around 1.35 μm. Combining the possible larger process variations caused by the reduced feature size and thinner junction barrier layer, operation of DEMUX and MUX circuits at 50 GHz is taken as a reasonable and challenging design goal.
20 GHz multiplexers (8:1, 4:1 and 2:1) and 20 GHz demultiplexers (1:8, 1:4 and 1:2) were designed and fabricated using the 1 kA/cm2 process. With the external test equipment, the correct functioning of a 1:4 DEMUX was observed up to 9.2 GHz. 3.5 GHz testing result has been achieved for a 2:1 MUX. When the designs were migrated to 50 GHz using a 6.5 kA/cm 2 process, all the circuit components were re-optimized for the new process and higher operation speed. A few specialized optimization tools were used to maximize the circuit parameter margins and yields. It was found that it is necessary to do post-layout re-optimization including parasitic inductances. Monte Carlo analyses based on process variations were performed to predict the circuit yield and timing variations.
When the clock speed is above 20 GHz, RSFQ circuit verifications using the external test equipment are not feasible due to the unavailability of room temperature test equipment and heavy dispersion along the cables. A data-driven-self-timed (DDST) on-chip test system was re-designed and optimized at 50 GHz assuming a 6.5 kA/cm2 process.
The 50 GHz 2-bit DEMUX, basic cells of the MUX and the high-speed test system layouts were fabricated in the UCB 6.5 kA/cm2 process. But due to an irreparable failure of the fabrication process, the chips could not be verified by testing.