In this thesis, Double Gate (DG) MOSFET technology is studied and subsequently some useful applications are proposed based on the studies performed as described.

When conventional MOSFET technology becomes harder and harder to scale down in size, DG MOSFET is believed to be a substitute as it can provide lower Threshold Voltage (V_T) and higher on/off current ratio through gate coupling effect. A simple process for planar DG MOSFET with two separated gates is proposed and fabricated for study purpose. DG MOSFET properties are found when comparing with other Single Gate (SG) devices being fabricated together. As only self-aligned DG MOSFET will be attractive to industrial demand, a self-aligned DG MOSFET process is proposed and fabricated based on previous process fabrication experiences. To further increase the circuit density, a 3-D CMOS inverter, with DG PMOS sitting on top of SG NMOS, is also proposed and fabricated. A 60% area reduction is found when comparing it to the conventional CMOS inverter.

As interconnect RC delay has become the major limitation in Integrated Circuit (IC) performance, 3-D ICs are so believed to be the future trend to reduce the interconnecting loading by allowing shorter connection path. A local-clustering technology is proposed based on the fabricated 3-D CMOS inverter. Simulation results show that significant reductions in interconnect loading; critical path delay and circuit area are achieved in local-clustering 3-D circuits without causing additional temperature rise.

Conventional FLASH memory is difficult to scale down due to the conflicting requirements on gate oxide thickness from SCEs control and data retention respectively. An original Opposite Side Floating Gate (OSFG) FLASH memory is proposed based on the study of gate coupling effect through fabricated DG MOSFET devices. The operations of 50nm OSFG-FLASH cells, including reading, programming, erasing and disturbs, are discussed in detail and demonstrated through simulation.