Technology scaling has enabled faster designs operating at very high clock frequencies and higher circuit densities leading to increased active power dissipation. Transistor scaling also results in increased leakage power dissipation and creates reliability issues arising from process variations. Of particular concern is the impact of device variability on circuits with critical timing races. This dissertation develops circuit architectures that eliminate the critical timing races for these circuits. The proposed solutions have similar performance and lower static and dynamic power consumption than the conventional approaches.

Dynamic NOR-NOR programmable logic arrays (PLAs) are fast and regular in structure. However, they have high power dissipation and suffer from an inherent critical timing race that increases design effort, primarily due to the need to maintain circuit robustness in the presence of variations. In this work, a novel PLA architecture which implements the AND plane as a hierarchical combination of dynamic NAND gates and retains the dynamic NOR gate based OR plane is presented. The NAND-NOR PLA architecture completely eliminates the critical timing race and has 43% lower active and 18% lower static power dissipation than the conventional PLA as demonstrated on an optimized design fabricated on a foundry 130 nm low standby power process. The fabricated circuits have been tested fully functional on silicon demonstrating a maximum operating frequency of 1.61 GHz at 1.6 V. Variation studies on the conventional PLA is performed using Monte-Carlo simulations.

This work also presents a novel dynamic word line decoder which is fast, has reduced active and leakage power dissipation compared to its conventional counterpart, and also enables faster race-free sense timing. In a 16 bank memory array, the energy-delay product of the dynamic decoders is 66% lower than that of a low power static version. The design leverages the predictability of dynamic circuits to provide significant decoder leakage reduction in unselected banks. The dynamic decoder has been fabricated on a 90 nm bulk CMOS process. The measured test chip address to word line delay is found to be 170 ps at 1.5 V and the measured leakage reduction over 20x at supply voltages greater than 0.8 V.