Advances in digital circuit technology lead to increasingly smaller transistors, faster clock speeds, and lower operating voltages. These factors contribute to a higher susceptibility to radiation (alpha and neutron), temperature (environment), power supply and ground noise, and electromagnetic interference. This sensitivity is compounded by the increasing number and density of transistors in a design. This susceptibility can lead to soft errors.

This thesis follows the path of radiation induced soft errors from generation to elimination. The path begins with an investigation and summary of the primary mechanisms of soft error creation: neutron and alpha radiation. We then climb a rung in the design hierarchy and discuss the structural level simulation of single event upsets and the large impact that parameter variation can have. The next investigation is another step up the design hierarchy to the register transfer level. We describe a soft error simulation environment implemented in Verilog, a hardware description language. Next, we describe a method of translating error probabilities generated at the structural level into a probability distribution that can be used to increase accuracy and efficiency in soft error simulations at higher levels. In the chapter following that, we examine the effectiveness of a system level soft error mitigation technique when applied to individual gates. The last step, before the conclusion, is an investigation of a novel design technique that exploits the natural soft error reducing capabilities available to designers.

The size and complexity of modern digital circuit designs requires that we adopt a number of new approaches to address the problem of soft errors. The cost of examining every possible error has become too great. We show how it is beneficial, perhaps necessary, to combine elements of probability theory, statistical analysis methods, design of experiments methods, high performance computational techniques, hardware design methods, design verification methods, fault-modeling, fault emulation, hardware simulation, and software simulation to effectively understand and direct reliability research.