Abstract: Manufacturing process variations have emerged as the primary challenge to the technology scaling of CMOS devices and circuits in the sub-100nm regime. In the presence of process variations, device and interconnect parameters such as channel length, wire parasitics, etc., are modeled as random variables or spatial stochastic processes that vary across the sample space of the manufactured chips. Under such conditions, circuit performance characteristics like the voltage, delay, slew and power are also stochastic processes. Statistical timing and power analyses account for the impact of these random process variations and are thus highly important problems in the sub-100nm regime. These analyses require variational performance models for the circuit building blocks viz., interconnects, power grids and CMOS gates as a function of the process variables. In this dissertation, efficient and highly accurate methods are proposed to obtain L₂ (mean-square) optimal stochastic voltage, delay, slew and power models for interconnects, power grids and CMOS gates in the presence of process variations. The methods are based on representing the stochastic circuit response as an orthonormal polynomial series in a Hilbert space of the random process variables. In the case of interconnects and power grids, the voltage response coefficients are obtained by applying the Galerkin residual error minimization method to the state-space representation. In the case of CMOS gates, the coefficients of the delay, slew and power models are obtained using efficient response surface methods, which are based on interpolation on sparse quadrature grids. The proposed methods have been exhaustively applied to several industrial circuits and test cases, and the results show significant speed-ups of over two orders of magnitude (10X-100X) over the golden-standard Monte Carlo simulations for comparable accuracy.