Abstract: Behavioral synthesis is an automated design process that compiles functional and/or algorithmic descriptions into optimized hardware architectures and implementations. It has long been identified as one of the critical technologies for enabling the transition to a higher level of abstraction, which promises a drastic improvement in design productivity and a significant reduction in design errors. Unfortunately, it stumbled in its debut on the EDA marketplace during the mid-1990s and so far has had a limited adoption among chip designers. However, the design complexity of integrated circuit (IC) systems in nanometerscale technologies is outgrowing the capabilities of current design methods. With the billion-transistor chip on the horizon, designers are facing an extreme complexity that can no longer be efficiently managed by the traditional RTL-based flows. This brought about a renewed interest in behavioral synthesis, and innovations are required to tackle the new technical challenges. In this dissertation we focus on three aspects of the scheduling algorithms for behavioral synthesis: (i) unified performance-driven scheduling; (ii) integrated scheduling and time budgeting for power optimization; (iii) integrated scheduling and physical planning for interconnect-centric designs. These algorithms are applied at the scheduling and planning stage of a platform-based behavioral synthesis system, named xPilot, being developed at UCLA. Most of the existing behavior-level scheduling heuristics either have a limited efficiency in a specific class of applications or lack general support of various design constraints. To address this problem, we propose a new scheduler that converts a rich set of scheduling constraints into a system of difference constraints (SDC) and performs a variety of powerful optimizations under a unified mathematical programming framework. Experiments demonstrate that our SDC-based scheduling technique provides efficient solutions for a broader range of applications with a higher quality of results (16% latency improvement) when compared to state-of-the-art scheduling heuristics. Power-efficiency is emerging as a first-order design metric in nanometer-scale IC designs. We propose an integrated scheduling and time budgeting technique which efficiently exploits the timing slacks available in the system to reduce circuit power consumption without significantly degrading the system performance. Given an overall latency constraint and a collection of convex power-delay tradeoff curves for each type of operation, our scheduler can intelligently schedule the operations to appropriate clock cycles and simultaneously select the module implementations that lead to low-power solutions. Experiments demonstrate that our proposed technique outperforms the maximum weighted slack approach by 28% on average in terms of total power consumption. Nanometer IC design also faces the interconnect performance limitation. Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz IC designs. For synchronous design, this requires the consideration of on-chip multicycle communication at the high level. We present a regular distributed register micro-architecture and an integrated scheduling and physical planning technique to directly allow multicycle communication and enable concurrent computation and communication. Experiments on data-flow-intensive designs show that we can achieve a clock period improvement of 44% and a total latency improvement of 37% on average compared to the conventional approach.