In this thesis study, a general synthetic procedure of Si nanowires combining electron beam patterning, solid phase crystallization (SPC) and dry etching is developed. The achieved polycrystalline Si nanowire arrays have precise dimensional, positional, orientation and length control. The potential application of these SPC Si nanowires to Schottky barrier field effect transistors (SBFETs) is studied. To get better device performance in these Schottky barrier field effect transistors, it is imperative to understand how different material, contact and nanowire length parameters affect the electrical transport mechanism in the metal contact/Si nanowire/metal contact structure. In order to achieve this goal, computer simulation is conducted on this structure with the aid of AMPS (Analysis of Microelectronic and Photonic Structures) program.

To explore the feature size effect on solid phase crystallization, SPC Si nanowire doping efficiency is compared with SPC Si thin films with the same doping and annealing conditions by resistivity measurement. Results show that as feature size shrunk, the doping efficiency gets poorer and poorer. It suggests that more grain boundary area, surface defect states and/or intragranular defect states might exist in one dimensional nanowires than 2 dimensional thin films. Two kinds of transistor structure, top gated and back gated, are fabricated and electrical characterization measurements are conducted on them. Results show that in our case, top gated “spacer” structure is not a good choice for SBFET due to the poor control of gate over channel current and low carrier mobility in SPC Si nanowires. On the contrary, back gate showed efficient control of the channel current. An extensive electrical characterization is conducted on the back gated SBFETs fabricated from SPC nanowires with three different SPC annealing temperatures. These SPC silicon nanowire transistors need low threshold voltage to be turned on and achieved a current on/off ratio of about 10³. However, their field effect mobilities are very low, suggesting small grain sizes and high defect states in SPC Si nanowires. Transistor performances are compared between these three groups of nanowires and the effect of annealing temperature on solid phase crystallization mechanism in Si nanowires is explored. As the SPC annealing temperature increases, the subthreshold slope gets improved, suggesting the decrease of trap states in the channel. Results also show that it is the grain boundary scattering, not surface scattering that dominate the electrical property in our SPC Si nanowire transistors.