Abstract:

With the migration to Deep Sub-Micron (DSM) process technologies, the power consumption of a circuit has come to the forefront of concerns and as a result, the power has become a critical design parameter. This work presents a novel High-Level Synthesis (HLS) methodology, called Power Islands , that eliminates the Spurious Switching Activity (SSA) and the leakage in a great portion of the resulting circuit by partitioning it into islands. Each island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all of the logic contained within it is idling. The partitioning is done in such a way that the components with maximally overlapping lifetimes are placed on the same island. By powering down an island during its idle cycles: (1)?the spurious switching that results from the broadcast to idle components is silenced and (2)?the power consumption due to leakage in inactive components is eliminated.

During the execution cycle of a synthesized design, each component is either active (performing a computation) or idle. Similarly, each register is either alive or dead. In previous generations of synthesized designs, all components (active or idle) and all registers (alive or dead) remained on and consumed power the entire time during the execution. However, our synthesis tool constructs design architectures in such a way that idle functional units and dead registers can be powered down for maximum possible number of cycles. During the other cycles of execution they remain on.

Our HLS process consists of Control Data Flow Graph (CDFG) extraction from the given Intermediate Format (IF), scheduling, resource binding, power island partitioning, register binding, interconnect allocation and data-path and controller generation tasks. Verilog is used as the Hardware Description Language (HDL) for Register Transfer Level (RTL) design representations.

Our HLS methodology is entirely implemented in C++. The RTL representations synthesized by our HLS tool are translated into the gate-level designs using Cadence's RT Compiler. Subsequently, Cadence's placement and routing tool, Encounter, is used to obtain the layout-level representations. Extracted transistor and capacitor net-lists from the layout are simulated using Cadence's transistor-level simulators Spectre or Ultrasim to measure and report the power consumption. A 65-nm process technology along with Berkeley's Predictive Technology Model (BPTM) containing CMOS device parameters for this particular feature size is also used.

Experiments showed significant savings in power due to Power Islands . We can safely project that as long as CMOS is the underlying choice of process technology for IC designs, with the migration to much smaller geometries where leakage becomes hard to control, significantly more savings can be gained from our approach.