As CMOS technology scales to deeper sub-micron generations, a host of challenges have emerged that may put an end to Moore's Law progress of integrated circuits systems. To a large degree, these challenges stem from the saturation in performance of intrachip metal wires, especially the long global wires on the chip. This work undertakes a comprehensive evaluation of the intrachip global interconnect problem, and develops a composite analysis framework that integrates multiple levels of abstraction. These include device-, circuit-, system-, and architecture-levels, which are interlinked to predict and isolate the nature of the most problematic interconnects in context of future technologies. We develop metrics that simplify the understanding of interplay between various modeling tiers in an effort to paint a credible picture of the future. It is shown that the global interconnects present an insurmountable roadblock to the current design paradigm, and will change the way we view the progress of integrated circuits systems. Optical interconnects have been under consideration as possible candidates to replace the problematic global wires. To this end, a concept optical link is designed and analytically modeled for intrachip application and is shown to offer significantly improved performance in comparison to metal. At the system-level, a multi-scale free space optical interconnection system is shown by analysis and experiment to have the link density and configuration flexibility to meet the performance requirement for intrachip global communication for future technologies. For experimental validation of the system, micro-optical elements are designed and fabricated in Silicon using true gray-scale lithography and ICP etching. For on-chip light sources and detectors, a new planar light coupling structure is designed, simulated, and fabricated to realize the integration of multiple-quantum-well-modulators (MQWMs) with a CMOS chip. These structures along with hybrid integrated MQWM arrays may serve as the enabling technology to realize cost-effective and high-performance solutions to the intrachip global communication problem.