Abstract: Silicon carbide (SiC) is a very promising semiconductor material for high temperature, high power applications due to its inherent physical and electronic properties. However, crystal defects in SiC wafers are considered to be one of the biggest roadblocks to further development. The effects of several types of morphological defects on the electrical properties of 4H-SiC Schottky devices were investigated. Micropipes and triangular defects with 3C inclusions degrade both breakdown voltage and barrier height. Other commonly found morphological defects, such as 'carrots' and oval-shaped pits do not affect breakdown voltage, although they sometimes still lower the barrier height and increase the reverse leakage current to varying degrees. Some morphological defects were correlated to the crystal defects underneath them. Statistical studies of various dislocations show that screw and basal plane dislocations degrade the breakdown voltage of 4H-SiC Schottky diodes, and isolated threading edge dislocations have negligible effects. A dislocation-based model was developed to explain the forward and reverse I-V characteristics of 4H-SiC Schottky diodes. It is based on two parallel interacting Schottky rectifiers with different Schottky barrier heights, where the lower Schottky barrier height is due to screw or basal plane dislocations. The impact of high temperature annealing using graphite encapsulation on the electrical properties of Ni Schottky diodes formed on the annealed surfaces is studied. Annealing for 10 minutes at temperatures up to 1800°C with graphite encapsulation actually reduces the high-current ideality factor of the diodes while raising the barrier height inferred from current-voltage measurements. Atomic force microscopy images of the annealed samples show no significant surface roughening, and the graphite can be removed after processing. Formation of I₁ Shockley stacking faults in 4H-SiC p-i-n diodes under high forward current stress is studied in diodes on both c-oriented and a-oriented substrates. The forward voltage increases during stressing for both orientations, accompanied by nucleation and expansion of faults visible in electroluminescence imaging. The formation of stacking faults of various shapes is explained for c-plane 4H-SiC p-i-n diodes, and the nature of the stacking faults is discussed. Movement of partial dislocations and stacking fault expansion were also observed during optically-induced degradation.