Abstract: Interconnection networks are replacing throughput-limited shared buses and dedicated wires in a wide range of parallel systems. Improvements in lithographic technologies that are allowing further miniaturization of silicon structures, and system frequencies and communication bandwidths to keep increasing, have also led to interconnection networks consuming a significant amount of power. This thesis tackles the power-performance of interconnection networks along two dimensions. At run-time it proposes two power management techniques for improving the power efficiency of interconnection networks. At design-time it presents a framework that can rapidly explore on-chip network power-performance tradeoffs as CMOS process technologies scale. The first power-management technique presented in this thesis proposes a design methodology for constructing self-regulating on/off interconnection networks. These networks possess communication links that autonomously switch on/off in response to run-time variations in traffic. The second technique uses static analysis at compile-time to estimate link utilization. Based on this analysis it then generates software directives that dynamically tune network link voltage and frequency transitions at run-time to save power. These techniques exhibit up to 76.3% power savings with small latency increases. Next, this thesis proposes system-level roadmapping for networks-on-chips (NoCs). As on-chip resources keep increasing, NoCs will be adopted by more chip multi-core systems, while the range of applications will keep expanding. To help designers prune the expanding design space of NoCs and choose the most suitable architectural configurations that balance NoC power-performance tradeoffs, this thesis presents Polaris, a design-time framework for projecting future state-of-the-art NoCs. Polaris uses as inputs synthetically generated traffic traces to drive its high-level design-space exploration toolchain that consists of 10s of thousands of NoCs, providing power/area/delay results for each such design point. Finally, motivated by the need for an accurate traffic model and generator for Polaris, this thesis proposes an empirically-derived traffic model for NoCs that comprehensively captures the spatio-temporal characteristics of NoC traffic with less than 5% error when compared to real traffic traces. Trident, the proposed traffic generator tool, then feeds synthetically generated traffic classes into Polaris, constituting a vital first step towards unraveling interconnect power-performance issues.