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Analysis, measurement and optimization of jitter in phase-locked loops
by Vamvakos, Socrates D., PhD, UNIVERSITY OF CALIFORNIA, BERKELEY, 2005, 0 pages; 3211551
 

Abstract: Phase-locked loops (PLLs) are key building blocks in computing and communication systems, where they are used to generate accurate timing signals. Due to the continuous increase in computation speeds and communication rates, PLLs are required to meet increasingly stringent jitter specifications. The ability to accurately analyze and predict PLL jitter behavior is very important; it is also vital to develop practical methods and techniques, which guarantee optimal PLL jitter performance under any operating conditions. The conventional approach to theoretical jitter analysis assumes a continuous-time, linear, time-invariant model for the PLL. However, continuous-time analysis does not capture certain aspects of PLL jitter, such as aliasing. Furthermore, the contribution of supply/substrate or device noise on PLL output jitter depends on the time instant, when the noise is applied. This is an effect that cannot be explained by a time-invariant PLL model. This work develops a discrete-time, linear, cyclostationary PLL model, which naturally models PLL jitter aliasing behavior and accounts for the time-varying nature of PLL noise sources. The theoretical results are verified through simulations. An adaptive PLL architecture is studied, which allows PLL jitter optimization by using on-chip jitter measurement circuitry. This architecture minimizes jitter by adjusting the loop parameters of the PLL, thus compensating for process variations, environmental noise and changes in the operating frequency. A theoretical and experimental approach is used to study the design issues and performance of such a system, especially regarding the accuracy and limitations of the on-chip jitter estimation circuitry and algorithm. The noise sources that affect the on-chip jitter measurement procedure are explained and analyzed and improved design solutions are proposed. The PLL with the jitter measurement circuitry is fabricated in a 0.13 μm CMOS process, and silicon measurements are obtained, which verify the theoretical predictions.

 
Advisor: Nikolic, Borivoje
School: UNIVERSITY OF CALIFORNIA, BERKELEY
Source: DAI-B 67/04, p. 2161, Oct 2006
Source Type: PhD
Subjects: Electrical engineering
Publication Number: 3211551
     
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