Abstract:

This thesis studies several important problems in VLSI system design related to low power, reliability and security. In order to answer this question, we provide several novel ideas at five design levels, namely, device level, circuit level, architecture level, algorithm level, and architecture and algorithm co-design.

It is well-known that rapidly evolving silicon technology creates smaller and faster CMOS transistors, with decreasing switching power. At a first sight, technology works for reducing power consumption. However, die area is not shrinking with technology (in other words, chips pack a quadratically increasing number of transistors). This would not be a problem if the power dissipation of basic CMOS gates decreased fast enough to compensate the increase in integration density. Unfortunately, power consumption arises as a third axis in the optimization space in addition to the traditional speed (performance) and area (cost) dimensions.

Existing low power design techniques do not significantly lower the power consumption of the chip; nor do they consider some new phenomenon caused by application of novel CMOS technologies, for example, gate leakage current caused by high-? gate dielectric. Low power design techniques should be refreshed with consideration of the new phenomenon. Furthermore, traditional low power techniques caused some significantly effects to the chip reliability and security, which were not well studied yet. In this thesis, we analyze some harmful effects of low power techniques to system reliability and proposed some methodologies to enhance the system reliability level while reducing significant power consumption. For system security, we propose Dynamic Voltage and Frequency Scaling (DVFS) as a novel method to prevent sensitive embedded processor from popular power attacks which are real thread to the secure processor.

More specifically, this thesis is divided into five parts to illustrate the above ideas. First, we studied leakage power and reliability at the device level by realizing a novel low-leakage reliable SRAM cell design, i.e., Hybrid high-? gate dielectric and jointly-biased gate and substrate SRAM (HSRAM) cell to suppress leakage current and enhance the resistance to soft error. At the circuit level, the thesis presents an accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits. The best input vector control method was reconsidered by adding the important gate leakage component. At the architecture level, we engineered power attack resistance for a novel CryptoSystem-On-a-Chip (cSOC) by considering the effects on power attacks of some intrinsic features of the cryptoprocessor core inside the cSOC, such as multiple-issue-width and leakage power scaling. We use Dynamic Voltage and Frequency Switching (DVFS) units in the cSOC to make the CPU more resistant to power attacks. At the algorithm level, the thesis presents a reliability characterization model. Then based on this model, we use reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip design. We use voltage island partitioning for System-On-a-Chip (SOC) and DVFS as case studies for this methodology. Finally, we consider an architecture and algorithm co-design by using motion estimation as an example.