Abstract: Two of the biggest challenges within the field of nanoelectronics are how to fabricate arrays of high-quality semiconducting nanowires (NWs) at narrow pitch, and how to address an individual NW within the array. Of the available means of fabricating NW arrays, only the superlattice nanowire pattern transfer (SNAP) method has produced arrays of NWs > 100 μm long and at narrow pitch. However, to date, conducting Si SNAP NW arrays have only been feasible down to a wire width of 50 nm, yielding a minimum pitch of ∼60 nm with no means of selecting individual NWs within the array. Here, I show that the SNAP technique can be used to produce conductive arrays of Si NWs down to 10 nm in width and at 35 nm pitch using appropriate starting material, careful reactive-ion etching, and spin-on doping. I also show that field-effect transistors with dielectrics of varying thickness and dielectric constant can be used as a scalable means of electrically addressing a single NW from within a NW array at a pitch unobtainable by conventional lithography.