Abstract:

As the technology scales down and the number of circuits grows, the issue of soft errors and reliability in system design is set to become an increasingly challenging issue for the industry as a whole. This is true for both commercial consumer applications and safety critical real-time applications. Specifically, for high-volume low-margin consumer products, frequent soft errors can lead to expensive field maintenance. For safety critical applications, on the other hand, poor reliability can be catastrophic in terms of both human and equipment cost. Therefore, reliability-aware design that targets at mitigating the potential consequences of soft errors (and other types of transient errors) is highly desirable. This thesis is a step in this direction. Specifically, we incorporate the reliability metric into the system level design process for embedded systems. Focusing on hardware/software co-design flow, this thesis proposes several techniques at different levels to improve design reliability. We first present a reliability oriented hardware/software co-design framework. We then propose two high-level synthesis techniques to improve the design reliability using a characterized library. We also incorporate energy consumption of the tasks mapped onto the multiprocessor architectures as softwares along with reliability metric. Since the memory components are more vulnerable to soft errors, we present a novel memory minimization strategy based on recomputation of select tasks. Finally, in this thesis, we also study the process mapping onto FPGAs (Field Programmable Gate Arrays) to improve the reliability of FPGA based designs.