As the number of cores on a chip continues to increase, the communication bottleneck between cores has become a critical issue. As traditional electrical networks on chips cannot meet the predicted bandwidth requirements without power consumption that goes beyond budget, alternative communication mediums have been proposed. As a potential solution, recent advances in silicon photonics have allowed the vision of on-chip photonic communication, and many on-chip photonic interconnection designs have been proposed in recent years. However, many of these have high complexity cost from trying to accomplish full 2D photonic routing over the chip area. The detailed physical implications of these complexities are often ignored in the research projects, and hence they fail to demonstrate realistic performance. The Photonic Networked Processor Array (P-NePA) presented in this thesis proposes an alternative approach, where a network is divided into smaller subnets. Full photonic connectivity is provided within each subnet, and the connections between subnets are accomplished through simple electrical routing and re-modulation of messages. It is demonstrated that P-NePA will likely result in small power consumption, area, and insertion loss compared to the other photonic networks, and P-NePA demonstrates good performance that does not degrade with high traffic, making it a viable solution to the problem of congestion in electrical networks.