Field-programmable gate array implementation of a scalable integral image architecture based on systolic arrays
by De la Cruz, Juan A., M.S., UTAH STATE UNIVERSITY, 2011, 61 pages; 1488995

Abstract:

The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, with some additional resources used in the Field Programmable Gate Array (FPGA), a speed increase is obtained by using a one-dimensional Systolic Array (SA) approach. Additionally, extra guidelines are given for further research in this area.

 
AdviserPaul Israelsen
SchoolUTAH STATE UNIVERSITY
SourceMAI/ 49-04, p. , Mar 2011
Source TypeThesis
SubjectsComputer engineering
Publication Number1488995
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