As the technology advances, the sensitivity of CMOS circuits to transient pulses caused by Single Event is progressively worsened. Although hardening techniques have been developed to address the problems associated with Single Event Transients for CMOS logic, the circuit interconnects are left vulnerable. As CMOS technology scaling continues, the Single Event Transients may cause noise contamination on electronically unrelated circuit paths due to increased coupling effects, which can in turn increase the "Single Event Susceptibility" of nanometer CMOS circuits. Serious effects may occur if the line is a part of clock network or the input line of voters in TMR circuit. Additionally, if Single Event crosstalk pulse is injected to victim line during line switching, it can cause delay changes on the victim wire and may violate setup and hold time requirements of logic storage circuits. In this thesis, the Single Event induced crosstalk noise and delay effects are investigated and suitable hardening techniques for Single Event Crosstalk are proposed for the first time. Results are demonstrated using HSpice Simulations with interconnect and device parameters derived in 65 nm, 90 nm and 130 nm technologies.