The increase in wire delay because of cross-coupling noise has dramatic effects on microchip performance for today's deep sub-micron technologies. Calculation of coupling induced delay using a traditional circuit simulator is computationally inefficient, and hence, alternative prediction models are being sought.

This study focuses on the various methods to estimate the delay in deep submicron architectures. In this work, we developed two methods to estimate crosstalk induced delay. In the first method, we developed closed form expressions for crosstalk delay in the presence of crosstalk while considering the effect of slew rates, driver strengths, and coupling capacitances.

The second method focuses on crosstalk delay estimation by revisiting the switch factor methodology using realistic exponential function, which closely resembles the real world signals. Here, the conclusion is made that (-1, 3) are the SF bounds for the worst and best cases for exponential functions. Considering these two cases, I performed simulations in HSPICE and obtained an average error of 11.8% on worst case and 6.8% on best case. This model is useful as a quick reference in verifying the percentage of nets in a certain range and to analytically decide the crosstalk induced delay in sub-micron processes.