Historically, the microelectronics industry has scaled down CMOS transistor dimensions in order to increase operating speeds, decrease cost per transistor, and free up on-chip real estate for additional chip functions. There are numerous challenges involved with scaling transistors down to the near term 32 nm node, and beyond. These challenges include short gate lengths, very thin gate oxides, short channel effects, quantum effects, band-to-band tunneling from source to drain, Gate Induced Drain Leakage, Fowler-Nordheim tunneling, and increasing dopant concentrations.
Field effect transistor circuits augmented with tunnel diodes lead to decreased circuit footprints, decreased device count, improved operating speeds, and lower power consumption without the need to solve current CMOS scaling challenges. Recently, N-on-P Si/SiGe resonant interband tunnel diodes (RITD) have been monolithically integrated with CMOS transistors. To further improve the benefits of RITD augmented circuits, P-on-N RITDS and all-Si RITDs were developed. Reported maximum peak-to-valley current ratios (PVCR), a key quantitative parameter of TDs, of 1.32 and 3.02 were measured, respectively.
Since integrated circuits operate at elevated temperatures, the I-V characteristics of various TDs were measured at temperatures ranging from room temperature up to 200°C. Three figures of merit were extracted; (i) peak current density (JP), (ii) valley current density (J V), and (iii) PVCR. Normalizing over their respective values at room temperature allowed for direct comparison between the various TD structures. This method allowed the author to determine that all devices show a similar JP response. However, the Si/SiGe RITD structure was overall least sensitive to temperature variations.
Furthermore, to design and optimize TD augmented circuits, a SPICE compatible model was developed. Past models have discontinuities, kinks in their slopes, difficult parameters to extract, unknown parameters, no closed form solutions, and/or poor fits to measured data. For this work a modified version of the S. M. Sze model with a superior match to experimental data, for Si based Esaki tunnel diodes (ETD) was developed. Using the developed model, several circuits were simulated, which were broken up into two groups. The first group of circuits is comprised of one TD and one of the following; (i) resistor, (ii) NMOS transistor, or (iii) TD. Finally, the behaviors learned from the simple circuits were used to simulate several TD augmented circuits such as (i) ADC comparator, (ii) TSRAM, (iii) and four basic logic gates.